The present disclosure relates generally to semiconductor devices, and more particularly to forming isolation regions adjacent to semiconductor devices that include threshold voltage modifications.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). With scaling of electrical devices potentially reaching their limits, other means of modifying device performance have been contemplated.